FIGS. 1-3, related to U.S. Pat. No. 5,120,671 to Tang et al., issued Jun. 9, 1992, show high density self-aligned-source flash memory cells fabricated by using a conventional process. FIG. 1 is a plan view of a portion of a memory device formed in that manner. Field oxide regions 10, 12 are formed as continuous lines across the source line 14 in the substrate 15. Using conventional techniques, a gate oxide layer is formed on the substrate areas between field oxide lines, followed by deposition and patterning of a first polysilicon layer, and formation of an intergate dielectric layer. A second layer of polysilicon 16 is deposited and, after appropriate masking, exposed portions of the polysilicon are etched away forming control gate regions 18, 20 (word lines). At this point, appropriate etching steps are used to remove intergate dielectric and first polysilicon exposed between word lines. A photoresist mask exposing the source regions is then applied over the device. Exposed field oxide regions 10, 12 are etched away using an oxide etch process selective to silicon, forming a source line connecting source regions 14. This continuous source line is parallel to and self-aligned to the edges of the previously defined word lines.
FIGS. 2 and 3 are sectional views taken along the lines 2--2 and 3--3 of FIG. 1 respectively, prior to the etching of the field oxide regions 10, 12. FIG. 2 shows a first stack 22 made up of gate oxide 24-floating gate 26-intergate dielectric 28-control gate 30, and a second stack 32 made up of gate oxide 34-floating gate 36-intergate dielectric 38-control gate 40 with source 42 and drains 44, 46 in the substrate 48 self-aligned to the edges of the control gates 30, 40. The word lines 18, 20 define the control gates 30, 40 respectively and extend over the field oxide regions such as regions 10, 12 (FIG. 3).
During the etching of field oxide regions 10, 12, it is inevitable that etchant reaches the silicon substrate 48 and causes gouging thereof in the regions between stacks 30, 40. Such gouging affects the formation of the source junction 42 causing the erase function to slow down, and can cause the erase distribution to be widened due to nonuniformity of such gouging from transistor to transistor.
In order to overcome the above-cited problem, the process as shown in FIGS. 4 through 9 has been used. (FIG. 4 includes sectional views 4a, 4b, and 4c, FIGS. 4a and 4b corresponding to the sectional views of FIGS. 2 and 3, while FIG. 4c is a sectional view of a periphery transistor in the same intergated circuit. FIGS. 5-9 follow the same convention, as do FIGS. 10-14).
As shown in FIG. 4a, a silicon substrate 130 is provided with a gate oxide 132 formed thereover. A first floating gate 134-intergate dielectric 136-control gate 138 stack 140 is provided on the oxide layer 132, and a second floating gate 142-intergate dielectric 144-control gate 146 stack 148 is also provided on the oxide layer 132, spaced from the stack 140. A source region 150 is provided in the substrate 130, self-aligned to the adjacent edges of the stacks 140, 148. Drain regions 152, 154 are also included in the substrate 130, self-aligned to the respective opposite edges of the stacks 140, 148. The control gates 138, 146 extend over field oxide 156 (FIG. 4b), which in turn lies over substrate 130. Remote from the structure of FIGS. 4a and 4b is a high voltage periphery transistor 158 (FIG. 4c) including a gate oxide 160 on the substrate 130, and a gate 162, with lightly-doped source and drain regions 164, 166 being self-aligned to the edges of the gate 162.
Over this structure is deposited a thick (for example 3000 .ANG.) layer of oxide 168. This deposited oxide 168 is then anisotropically etched to form relatively wide spacers 170, 172, 174, 176 on the sides of each stack 140, 148, relatively wide spacers 178, 180 on the adjacent sides of the control gates 138, 146 over the field oxide 156, and relatively wide spacers 182, 184 on the sides of the gate 162 of the high voltage periphery transistor 158. The relatively wide spacers 182, 184 on the sides of the gate 162 of the high voltage periphery transistor 158 are properly configured so that subsequently-formed heavily doped source and drain regions will be self-aligned to the spacers 182, 184 and properly positioned in relation to the lightly doped source and drain regions 164, 166. Such wide spacers 182, 184 are necessary to meet high transistor junction breakdown requirements. However, provision of such relatively wide spacers 178, 180 on the inner sides of the control gates 138, 140 over the field oxide 156 causes certain problems, as will now be described.
As noted in FIG. 5, masking 186 is provided over appropriate areas of the structure, and further anisotropic etching is undertaken. Such etching is undertaken through the thin oxide layer 132 (FIG. 6a), and also through the field oxide 156 (FIG. 6b), it being noted that the exposed width (dimension X) of the silicon 130 due to etching through of the field oxide 156 is relatively small, because of the initial large width of the spacers 178, 180. In the meantime, etchant cannot reach the high-voltage periphery transistor 158 due to masking 186 thereover.
Then, after removal of the masking 186, a thin layer of oxide 188 is grown over the exposed portion of the silicon 130 between the stacks 140, 148, and a thin layer of oxide 190 is grown over the exposed portion of the silicon 130 provided by the opening in the field oxide 156 (FIG. 7b) simultaneously forming thin oxide layers 188, 190 and 191.
After further masking 192 (FIG. 8), ion implantation 194 is undertaken through the grown thin layers of oxide 188, 190, and a diffusion step is undertaken so that the source region 150 takes the shape shown in FIG. 9a, and the diffused area 196 adjacent the field oxide (FIG. 9b) provides connection between the source region 150 and other source regions. Further processing steps are then provided to form heavily doped source and drain regions 198, 200 of the periphery transistor 158, self aligned to the spacers 182, 184.
This method, because of inclusion of spacers 170, 172, 174, 176, avoids the gouging problem at the gate edges described above with regard to FIG. 1. However, with the very small dimension X as shown at FIG. 6b, the narrow connecting region results in high series resistance between devices.
In addition, it should be noted that for the process described, two masking steps are involved. It will be understood that is always desirable to decrease the number of masking steps in a process, so as to improve manufacturing efficiency.